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PRELIMINARY CY14B104L, CY14B104N
4-Mbit (512K x 8/256K x 16) nvSRAM
Features

Functional Description
The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K words of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world's most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.
15 ns, 25 ns, and 45 ns access times Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) Hands off automatic STORE on power down with only a small capacitor STORE to QuantumTrap(R) nonvolatile elements initiated by software, device pin or AutoStore(R) on power down RECALL to SRAM initiated by software or power up Infinite read, write, and recall cycles 8 mA typical ICC at 200 ns cycle time 200,000 STORE cycles to QuantumTrap 20 year data retention Single 3V +20%, -10% operation Commercial and industrial temperatures FBGA and TSOP - II packages RoHS compliance
Logic Block Diagram
VCC
VCAP
Address A0 - A18
CE OE WE
[1]
[1]
DQ0 - DQ7 CY14B104L CY14B104N HSB
BHE BLE
VSS
Note 1. Address A0 - A18 and Data DQ0 - DQ7 for x8 configuration, Address A0 - A17 and Data DQ0 - DQ15 for x16 configuration.
Cypress Semiconductor Corporation Document #: 001-07102 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 02, 2008
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PRELIMINARY CY14B104L, CY14B104N
Pinouts
Figure 1. Pin Diagram - 48 FBGA
48-FBGA
(x16)
48-FBGA
(x8)
Top View (not to scale)
1 BLE 2 OE 3 A0 A3 A5 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE 6 NC DQ0 A B C D E F G H
1 NC NC DQ0 VSS VCC DQ3 NC A18 2 OE NC NC DQ1
Top View (not to scale)
3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE NC DQ5 DQ6 NC WE A11 6 NC NC DQ4 VCC VSS DQ7 NC NC
[2]
A B C D E F G H
DQ8 BHE DQ9 DQ10 VSS
DQ1 DQ2 DQ3 DQ4 VCC VSS
DQ11 A17
VCC DQ12 VCAP DQ14 DQ13 DQ15 HSB NC
[2]
DQ2 VCAP NC HSB A8 A14 A12 A9
A14 A12 A9
DQ5 DQ6 WE A11 DQ7 NC
A8
Figure 2. Pin Diagram - 44 TSOP II
A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC [3] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 VCC VSS DQ2 DQ3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 HSB NC [2] NC A18 A17 A16 A15 OE DQ7 DQ6 VSS VCC DQ5 DQ4 VCAP A14 A13 A12 A11 A10 NC NC
44 - TSOP II
(x16)
44 - TSOP II
(x8)
Top View (not to scale)
Top View (not to scale)
Notes 2. Address expansion for 8 Mbit. NC pin not connected to die. 3. Address expansion for 16 Mbit. NC pin not connected to die.
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PRELIMINARY CY14B104L, CY14B104N
Pinouts
(continued) Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
NC [3] NC A0 A1 A2 A3 A4 CE DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A5 A6 A7 A8 A9 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 HSB NC [2] A17 A16 A15 OE BHE BLE DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 VCAP A14 A13 A12 A11 A10 NC NC NC
54 - TSOP II
(x16)
Top View (not to scale)
Pin Definitions
Pin Name A0 - A18 A0 - A17 DQ0 - DQ7
DQ0 - DQ15
IO Type Input
Description Address Inputs Used to Select one of the 524, 288 bytes of the nvSRAM for x8 Configuration. Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x16 Configuration.
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on operation. Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on operation. Input Input Input Ground Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the address location latched by the falling edge of CE. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. IO pins are tri-stated on deasserting OE high. Ground for the Device. Must be connected to the ground of the system.
WE CE OE VSS VCC HSB
Power Supply Power Supply Inputs to the Device. Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin HIGH if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from the SRAM to nonvolatile elements. No Connect No Connect. Do not connect this pin to the die. Page 3 of 22
VCAP NC
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Device Operation
The CY14B104L/CY14B104N nvSRAM is made up of two functional components paired in the same physical cell. They are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to the SRAM (the RECALL operation). Using this unique architecture all cells are stored and recalled in parallel. During the STORE and RECALL operations SRAM read and write operations are inhibited. The CY14B104L/CY14B104N supports infinite reads and writes similar to a typical SRAM. In addition, it provides infinite RECALL operations from the nonvolatile cells and up to 200K STORE operations.
To reduce unnecessary nonvolatile stores, AutoStore and Hardware Store operations are ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. Monitor the HSB signal by the system to detect if an AutoStore cycle is in progress. Figure 4. AutoStore Mode
V CC V CAP
V CAP
V CC
10k Ohm
SRAM Read
The CY14B104L/CY14B104N performs a READ cycle when CE and OE are LOW, and WE and HSB are HIGH. The address specified on pins A0-18 or A0-17 determines which of the 524,288 data bytes or 262,144 words of 16 bits each is accessed. When the read is initiated by an address transition, the outputs are valid after a delay of tAA (read cycle #1). If the read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (read cycle #2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins. This remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
WE
V CC V CC V CAP
V CAP
+ -
SRAM Write
A WRITE cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable before entering the WRITE cycle and must remain stable until either CE or WE goes high at the end of the cycle. The data on the common IO pins DQ0-15 are written into the memory if the data is valid tSD before the end of a WE controlled WRITE or before the end of an CE controlled WRITE. It is recommended that OE be kept HIGH during the entire WRITE cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
Hardware STORE Operation
The CY14B104L/CY14B104N provides the HSB pin for controlling and acknowledging the STORE operations. Use the HSB pin to request a hardware STORE cycle. When the HSB pin is driven LOW, the CY14B104L/CY14B104N conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a WRITE to the SRAM took place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition while the STORE (initiated by any means) is in progress. SRAM READ and WRITE operations that are in progress when HSB is driven LOW by any means are given time to complete before the STORE operation is initiated. After HSB goes LOW, the CY14B104L/CY14B104N continues SRAM operations for tDELAY. During tDELAY, multiple SRAM READ operations may take place. If a WRITE is in progress when HSB is pulled low it is allowed a time, tDELAY to complete. However, any SRAM WRITE cycles requested after HSB goes LOW is inhibited until HSB returns HIGH. During any STORE operation, regardless of how it was initiated, the CY14B104L/CY14B104N continues to drive the HSB pin LOW, releasing it only when the STORE is complete. Upon completion of the STORE operation, the CY14B104L/CY14B104N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.
AutoStore Operation
The CY14B104L/CY14B104N stores data to the nvSRAM using one of the following three storage operations: Hardware Store activated by HSB; Software Store activated by an address sequence; AutoStore on device power down. The AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the CY14B104L/CY14B104N. During a normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 4 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. Refer to the section DC Electrical Characteristics on page 7 for the size of VCAP.
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B104L/CY14B104N software STORE cycle is initiated by executing sequential CE-controlled READ cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed. Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other READ or WRITE accesses intervene in the sequence. If there are intervening READ or WRITE accesses, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following READ sequence must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x8FC0 Initiate STORE Cycle Table 1. Mode Selection CE H L L L WE X H L H OE X L X L
The software sequence may be clocked with CE controlled READs or OE controlled READs. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important to use READ cycles and not WRITE cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the READ and WRITE operation.
Software RECALL
Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled READ operations must be performed. 1. Read Address 0x4E38 Valid READ 2. Read Address 0xB1C7 Valid READ 3. Read Address 0x83E0 Valid READ 4. Read Address 0x7C1F Valid READ 5. Read Address 0x703F Valid READ 6. Read Address 0x4C63 Initiate RECALL Cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared and then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for READ and WRITE operations. The RECALL operation does not alter the data in the nonvolatile elements.
A15 - A0 X X X 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8B45 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4B46
Mode Not Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Disable Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM AutoStore Enable
IO Output High Z Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data
Power Standby Active Active Active[4,5,6]
L
H
L
Active[4,5,6]
Notes 4. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 5. While there are 19 address lines on the CY14B104L/CY14B104N, only the lower 16 lines are used to control software modes. 6. IO state depends on the state of OE. The IO table shown assumes OE LOW.
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PRELIMINARY CY14B104L, CY14B104N
Table 1. Mode Selection (continued) CE L WE H OE L A15 - A0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x8FC0 0x4E38 0xB1C7 0x83E0 0x7C1F 0x703F 0x4C63 Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Store Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile Recall IO Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Active ICC2[4,5,6]
L
H
L
Active[4,5,6]
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore disable sequence. A sequence of read operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore disable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x8B45 AutoStore Disable The AutoStore is re-enabled by initiating an AutoStore enable sequence. A sequence of read operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore enable sequence, the following sequence of CE controlled read operations must be performed: 1. Read address 0x4E38 Valid READ 2. Read address 0xB1C7 Valid READ 3. Read address 0x83E0 Valid READ 4. Read address 0x7C1F Valid READ 5. Read address 0x703F Valid READ 6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or re-enabled a manual STORE operation (hardware or software) must be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
Data Protection
The CY14B104L/CY14B104N protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and write operations. The low voltage condition is detected when VCC < VSWITCH. If the CY14B104L/CY14B104N is in a write mode (both CE and WE LOW) at power up, after a RECALL or STORE, the write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Noise Considerations
Refer CY Application Note AN1064.
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PRELIMINARY CY14B104L, CY14B104N
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +150C Supply Voltage on VCC Relative to GND ..........-0.5V to 4.1V Voltage Applied to Outputs in High-Z State....................................... -0.5V to VCC + 0.5V Input Voltage.............................................-0.5V to Vcc+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential .................. -2.0V to VCC + 2.0V
Package Power Dissipation Capability (TA = 25C) ................................................... 1.0W Surface Mount Pb Soldering Temperature (3 Seconds) .......................................... +260C Output Short Circuit Current [7] .................................... 15 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 2.7V to 3.6V 2.7V to 3.6V
DC Electrical Characteristics
Over the Operating Range (VCC = 2.7V to 3.6V)[8] Parameter ICC1 Description Average VCC Current Test Conditions tAVAV = 15 ns tAVAV = 25 ns tAVAV = 45 ns Dependent on output loading and cycle rate.Values obtained without output loads. IOUT = 0 mA All Inputs Don't Care, VCC = Max Average current for duration tSTORE Commercial Min Max 70 65 50 75 70 52 3 13 Unit mA mA mA mA mA mA mA mA
Industrial
ICC2 ICC3
Average VCC Current during STORE
Average VCC Current at WE > (VCC - 0.2). All other I/P cycling. tAVAV = 200 ns, 3V, Dependent on output loading and cycle rate. Values obtained without output loads. 25C typical Average VCAP Current All Inputs Don't Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current CE > (VCC - 0.2). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. -1 -1 2.0 Vss - 0.5 IOUT = -2 mA IOUT = 4 mA Between VCAP pin and VSS, 5V Rated 35 2.4
ICC4 ISB
3 2
mA mA
IIX IOZ VIH VIL VOH VOL VCAP
Input Leakage Current VCC = Max, VSS < VIN < VCC Off-State Output VCC = Max, VSS < VIN < VCC, CE or OE > VIH Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Storage Capacitor
+1 +1 VCC + 0.5 0.8 0.4 57
A A V V V V F
Capacitance
In the following table, the capacitance parameters are listed.[9] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 0 to 3.0V Max 7 7 Unit pF pF
Notes 7. Outputs shorted for no more than one second. No more than one output shorted at a time. 8. Typical conditions for the active current shown on the front page of the data sheet are average values at 25C (room temperature), and VCC = 3V. Not 100% tested. 9. These parameters are guaranteed but not tested.
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PRELIMINARY CY14B104L, CY14B104N
Thermal Resistance
In the following table, the thermal resistance parameters are listed. [9] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 48-FBGA 44-TSOP II 54-TSOP II TBD TBD TBD TBD TBD TBD Unit C/W C/W
JA JC
AC Test Loads
577 3.0V OUTPUT 30 pF R2 789 R1 577 3.0V OUTPUT 5 pF R2 789 R1
for tri-state specs
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PRELIMINARY CY14B104L, CY14B104N
AC Test Conditions
Input Pulse Levels ....................................................0V to 3V Input Rise and Fall Times (10% - 90%) ........................ <5 ns Input and Output Timing Reference Levels .................... 1.5V
AC Switching Characteristics
In the following table, the AC switching characteristics are listed. Parameters Cypress Parameters tACE tRC[10] tAA[11] tDOE tOHA tLZCE[12] tHZCE[12] tLZOE[12] tHZOE[12] tPU[9] tPD[9] tDBE tLZBE tHZBE tWC tPWE tSCE tSD tHD tAW tSA tHA tHZWE[12,13] tLZWE[12] tBW Alt Parameters tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS tWC tWP tCW tDW tDH tAW tAS tWR tWZ tOW Description 15 ns Min Max 25 ns Min Max 45 ns Min Max Unit
SRAM Read Cycle Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby Byte Enable to Data Valid Byte Enable to Output Active Byte Disable to Output Inactive Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active after End of Write Byte Enable to End of Write 3 15 15 10 15 5 0 15 0 0 7 3 20 0 7 25 20 20 10 0 20 0 0 10 3 30 0 15 10 0 10 45 30 30 15 0 30 0 0 15 0 7 0 25 12 0 22 3 3 7 0 10 0 45 22 15 15 10 3 3 10 0 15 15 25 25 12 3 3 15 25 45 45 20 45 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SRAM Write Cycle
Notes 10. WE must be HIGH during SRAM read cycles. 11. Device is continuously selected with CE and OE both LOW. 12. Measured 200 mV from steady state output voltage. 13. If CE is LOW and then WE goes LOW, the output goes into high impedance state afetr tHZWE time period.
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PRELIMINARY CY14B104L, CY14B104N
AutoStore/Power Up RECALL
Parameters tHRECALL [14] tSTORE [15] VSWITCH tVCCRISE Description Power Up RECALL Duration STORE Cycle Duration Low Voltage Trigger Level VCC Rise Time 150 CY14B104L/CY14B104N Min Max 20 15 2.65 Unit ms ms V s
Software Controlled STORE/RECALL Cycle
In the following table, the software controlled STORE/RECALL cycle parameters are listed.[16, 17] Parameters tRC tAS tCW tGHAX tRECALL tSS [18, 19] Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Soft Sequence Processing Time 15ns Min 15 0 12 1 100 70 Max 25 0 20 1 100 70 25ns Min Max 45 0 30 1 100 70 45ns Min Max Unit ns ns ns ns s s
Hardware STORE Cycle
Parameters tDELAY [20] tHLHX Description Time allowed to complete SRAM Cycle Hardware STORE Pulse Width CY14B104L/CY14B104N Min 1 15 Max 70 Unit s ns
Switching Waveforms
Figure 5. SRAM Read Cycle #1: Address Controlled[10, 11, 21]
tRC
ADDRESS
t AA t OHA
DQ (DATA OUT) DATA VALID
Notes 14. tHRECALL starts from the time VCC rises above VSWITCH. 15. If an SRAM Write has not taken place since the last nonvolatile cycle, no STORE takes place. 16. The software sequence is clocked with CE controlled or OE controlled reads. 17. The six consecutive addresses must be read in the order listed in the mode selection table. WE must be HIGH during all six consecutive cycles. 18. This is the amount of time it takes to take action on a soft sequence command.Vcc power must remain HIGH to effectively register command. 19. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command 20. Read and write cycles are in progress before HSB are supplied this amount of time to complete. 21. HSB must remain HIGH during READ and WRITE cycles.
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PRELIMINARY CY14B104L, CY14B104N
Switching Waveforms (continued)
Figure 6. SRAM Read Cycle #2: CE and OE Controlled[10, 21, 23]
tRC
ADDRESS
CE
tLZCE
tACE
tPD tHZCE
OE
tLZOE
BHE , BLE
tDOE
t HZOE
DQ (DATA OUT)
tLZBE t PU
tDBE
DATA VALID
tHZCE tHZBE
ACTIVE
ICC
STANDBY
Figure 7. SRAM Write Cycle #1: WE Controlled[21, 22, 23]
t WC
ADDRESS
t SCE
CE
t HA
t AW t SA
WE
t PWE
BHE , BLE
t BW t SD t HD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
t LZWE
Notes 22. CE or WE must be >VIH during address transtions. 23. BHE and BLE are applicable for x16 configuration only.
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PRELIMINARY CY14B104L, CY14B104N
Switching Waveforms (continued)
Figure 8. SRAM Write Cycle #2: CE Controlled[23]
tWC
ADDRESS
tSA
CE
tSCE tAW tHA tPWE
WE
BHE , BLE
tBW
tSD tHD
DATA VALID
DATA IN
DATA OUT
HIGH IMPEDANCE
Figure 9. AutoStore or Power Up RECALL
VCC VSWITCH
STORE occurs only if a SRAM write has happened
No STORE occurs without atleast one SRAM write
tVCCRISE
AutoStore
tSTORE
tSTORE
POWER-UP RECALL
tHRECALL
Read & Write Inhibited
tHRECALL
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PRELIMINARY CY14B104L, CY14B104N
Switching Waveforms (continued)
Figure 10. CE-controlled Software STORE/RECALL Cycle[17]
tRC tRC
ADDRESS ADDRESS ADDRESS # 1 ADDRESS # 1
tRC tRC
ADDRESS # 6 ADDRESS # 6
CE CE
tAS tSA
tCW tSCE tGLAX
OE OE
tGHAX
t STORE / t RECALL t STORE / t RECALL
DQ (DATA) DQ (DATA) DATA VALID DATA VALID DATA VALID DATA VALID
HIGH IMPEDANCE HIGH IMPEDANCE
Figure 11. OE-controlled Software STORE/RECALL Cycle[17]
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
CE
tAS
OE
tCW tGHAX
t STORE / t RECALL
DATA VALID
HIGH IMPEDANCE
DQ (DATA)
DATA VALID
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PRELIMINARY CY14B104L, CY14B104N
Switching Waveforms (continued)
Figure 12. Hardware STORE Cycle[20]
Figure 13. Soft Sequence Processing[18, 19]
tSS
tSS
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PRELIMINARY CY14B104L, CY14B104N
Ordering Information
Speed (ns) 15 Ordering Code CY14B104L-ZS15XCT CY14B104L-ZS15XIT CY14B104L-ZS15XI CY14B104L-BA15XCT CY14B104L-BA15XIT CY14B104L-BA15XI CY14B104L-ZSP15XCT CY14B104L-ZSP15XIT CY14B104L-ZSP15XI CY14B104N-ZS15XCT CY14B104N-ZS15XIT CY14B104N-ZS15XI CY14B104N-BA15XCT CY14B104N-BA15XIT CY14B104N-BA15XI CY14B104N-ZSP15XCT CY14B104N-ZSP15XIT CY14B104N-ZSP15XI 25 CY14B104L-ZS25XCT CY14B104L-ZS25XIT CY14B104L-ZS25XI CY14B104L-BA25XIT CY14B104L-BA25XI CY14B104N-BA25XCT CY14B104L-ZSP25XCT CY14B104L-ZSP25XIT CY14B104L-ZSP25XI CY14B104N-ZS25XCT CY14B104N-ZS25XIT CY14B104N-ZS25XI CY14B104N-BA25XCT CY14B104N-BA25XIT CY14B104N-BA25XI CY14B104N-ZSP25XCT CY14B104N-ZSP25XIT CY14B104N-ZSP25XI Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Commercial Industrial Commercial Industrial Commercial Industrial Commercial Commercial Industrial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Ordering Information (continued)
Speed (ns) 45 Ordering Code CY14B104L-ZS45XCT CY14B104L-ZS45XIT CY14B104L-ZS45XI CY14B104L-BA45XCT CY14B104L-BA45XIT CY14B104L-BA45XI CY14B104L-ZSP45XCT CY14B104L-ZSP45XIT CY14B104L-ZSP45XI CY14B104N-ZS45XCT CY14B104N-ZS45XIT CY14B104N-ZS45XI CY14B104N-BA45XCT CY14B104N-BA45XIT CY14B104N-BA45XI CY14B104N-ZSP45XCT CY14B104N-ZSP45XIT CY14B104N-ZSP45XI Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Industrial
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Part Numbering Nomenclature
CY 14 B 104 L - ZS P 15 X C T Option: T - Tape & Reel Blank - Std. Pb-Free Package: BA - 48 FBGA ZS - TSOP II
Temperature: C - Commercial (0 to 70C) I - Industrial (-40 to 85C)
P - 54 Pin Blank - 44 Pin
Speed: 15 - 15 ns 25 - 25 ns 45 - 45 ns
Data Bus: L - x8 N - x16
Voltage: B - 3.0V
Density: 104 - 4 Mb
NVSRAM 14 - Auto Store + Software Store + Hardware Store
Cypress
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Package Diagrams
Figure 14. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH) MAX MIN.
22 1
PIN 1 I.D.
11.938 (0.470) 11.735 (0.462)
10.262 (0.404) 10.058 (0.396)
OR E KXA SG
23
44
EJECTOR PIN
TOP VIEW
BOTTOM VIEW
0.800 BSC (0.0315)
0.400(0.016) 0.300 (0.012)
BASE PLANE 0-5 0.10 (.004)
10.262 (0.404) 10.058 (0.396) 0.210 (0.0083) 0.120 (0.0047)
18.517 (0.729) 18.313 (0.721) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) SEATING PLANE
0.597 (0.0235) 0.406 (0.0160)
51-85087-*A
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Package Diagrams
(continued) Figure 15. 48-ball FBGA (6 mm x 10 mm x 1.2 mm)
TOP VIEW
BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B
A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1
A B C 10.000.10 10.000.10 0.75 5.25 D E F G H
A B C D E 2.625 F G H
A B 6.000.10
A
1.875 0.75 3.75
0.530.05
0.25 C
B 0.210.05 0.15 C 0.15(4X)
6.000.10
SEATING PLANE 0.36 C 1.20 MAX
51-85128-*D
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Package Diagrams
(continued) Figure 16. 54-Pin TSOP II (51-85160)
51-85160-**
Document #: 001-07102 Rev. *F
Page 20 of 22
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PRELIMINARY CY14B104L, CY14B104N
Document History Page
Document Title: CY14B104L/CY14B104N 4-Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 REV. ** *A ECN NO. 431039 489096 Issue Date See ECN See ECN Orig. of Change TUP TUP New Data Sheet Removed 48 SSOP Package Added 48 FBGA and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform Removed 35 ns speed bin Added 55 ns speed bin. Updated AC table for the same Changed "Unlimited" read/write to "infinite" read/write Features section: Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles Shaded Commercial grade in operating range table Modified Icc/Isb specs 48 FBGA package nomenclature changed from BW to BV Modified part nomenclature table. Changes reflected in the ordering information table Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35F Changed VIH max to Vcc + 0.5V Changed tSTORE to 15ms Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min specification for Vswitch Changed tGLAX to 1ns Added tDELAY max of 70us Changed tSS specification from 70us min to 70us max Changed the data sheet from Advance information to Preliminary 48 FBGA package code changed from BV to BA Removed 48 FBGA package in X8 configuration in ordering information. Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW in 15ns part to15ns Changed A18 and A19 Pins in FBGA Pin Configuration to NC Description of Change
*B
499597
See ECN
PCI
*C
517793
See ECN
TUP
*D
774001
See ECN
UHA
Document #: 001-07102 Rev. *F
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PRELIMINARY CY14B104L, CY14B104N
Document Title: CY14B104L/CY14B104N 4-Mbit (512K x 8/256K x 16) nvSRAM Document Number: 001-07102 REV. *E *F ECN NO. 914220 1889928 Issue Date See ECN See ECN Orig. of Change UHA Description of Change Included all the information for 45 ns part in this data sheet
vsutmp8/AESA Added Footnotes 1, 2 and 3. Updated logic block diagram Added 48-FBGA (X8) Pin Diagram Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II (x8) package. Updated pin definitions table. Corrected typo in VIL min spec Changed the value of ICC3 from 25mA to 13mA Changed ISB value from 1mA to 2mA Rearranging of Footnotes. Updated ordering information table
(c) Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-07102 Rev. *F
Revised January 02, 2008
Page 22 of 22
AutoStore and QuantumTrap are registered trademarks of Simtek Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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